This invention relates to the fabrication of semiconductor devices and, more particularly, to a method for patterning the non-planar surface of a semiconductor wafer on which devices are to be made.
For a variety of applications of practical importance, it is necessary that a substrate having a non-planar surface topology be lithographically processed to define patterns on the surface of the wafer. Thus, for example, for making devices for use in an optical communication system, it may be necessary to define patterns on a semiconductor wafer having v-shaped grooves formed in its surface. In particular, patterns may have to be defined simultaneously both in the v-grooves and on adjacent planar portions of the wafer surface.
It is well known that considerable difficulties are associated with utilizing conventionally spun-on resists for patterning non-planar wafer surfaces. In particular, the presence of v-grooves in such a surface presents an overall wafer topology that cannot be uniformly coated with standard spin-on resist technology. In practice, a spun-on resist tends to form a coating along the edges of such grooves that is thin relative to some prescribed nominal coating thickness, while forming a considerably thicker-than-prescribed coating in low-lying areas of the grooves.
The aforedescribed non-uniform distribution of spun-on resist over the surface of a wafer containing v-grooves is clearly undesireable. The inevitable result of such non-uniform distribution is that it is difficult, if not impossible, in a wafer processing sequence to lithographically achieve well-defined and consistent resist patterns simultaneously both in the grooves and on adjacent planar surface portions of the wafer.
Accordingly, considerable efforts have been directed by workers skilled in the art aimed at trying to devise semiconductor device fabrication sequences, including resist-based lithographic steps, suitable for forming small-feature-size patterns on the non-planar surfaces of semiconductor wafers. It was recognized that these efforts, if successful, could improve the yield, lower the cost, and improve the performance and reliability of semiconductor devices whose manufacture on non-planar wafer surfaces has heretofore been considered exceedingly difficult and complicated.